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single, 3 v, cmos, lvds, high speed differential driver adn4661 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features 15 kv esd protection on output pins 600 mbps (300 mhz) switching rates flow-through pinout simplifies pcb layout 300 ps typical differential skew 700 ps maximum differential skew 1.5 ns maximum propagation delay 3.3 v power supply 355 mv differential signaling low power dissipation: 23 mw typical interoperable with existing 5 v lvds receivers conforms to tia/eia-644 lvds standards industrial operating temperature range (?40c to +85c) available in surface-mount (soic) package applications backplane data transmission cable data transmission clock distribution functional block diagram adn4661 v cc d in d out+ d out? gnd nc nc nc 07876-001 nc = no connect figure 1. general description the adn4661 is a single, cmos, low voltage differential signaling (lvds) line driver offering data rates of over 600 mbps (300 mhz) and ultra-low power consumption. it features a flow-through pinout for easy pcb layout and separation of input and output signals. the device accepts low voltage ttl/cmos logic signals and converts them to a differential current output of typically 3.1 ma for driving a transmission medium such as a twisted- pair cable. the transmitted signal develops a differential voltage of typically 355 mv across a termination resistor at the receiv- ing end, and this is converted back to a ttl/cmos logic level by a line receiver. the adn4661 and a companion lvds receiver offer a new solution to high speed point-to-point data transmission, and a low power alternative to emitter-coupled logic (ecl) or positive emitter-coupled logic (pecl).
adn4661 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 4 absolute maximum ratings ............................................................ 5 esd caution...................................................................................5 pin configuration and function descriptions ..............................6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 10 applications information .......................................................... 10 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history 12/08revision 0: initial version
adn4661 rev. 0 | page 3 of 12 specifications v cc = 3 v to 3.6 v; r l = 100 ; c l = 15 pf to gnd; all specifications t min to t max , unless otherwise noted. table 1. parameter 1 , 2 symbol min typ max unit test conditions lvds outputs (d out+ , d out? ) differential output voltage v od 250 355 450 mv see figure 2 and figure 4 change in magnitude of v od for complementary output states v od 1 35 |mv| see figure 2 and figure 4 offset voltage v os 1.125 1.2 1.375 v see figure 2 and figure 4 change in magnitude of v os for complementary output states v os 3 25 |mv| see figure 2 and figure 4 output high voltage v oh 1.4 1.6 v see figure 2 and figure 4 output low voltage v ol 0.90 1.1 v see figure 2 and figure 4 inputs (d in , v cc ) input high voltage v ih 2.0 vcc v input low voltage v il gnd 0.8 v input high current i ih ?10 2 +10 a v in = 3.3 v or 2.4 v input low current i il ?10 1 +10 a v in = gnd or 0.5 v input clamp voltage v cl ?1.5 ?0.6 v i cl = ?18 ma lvds output protection (d out+ , d out? ) output short-circuit current 3 i os ?5.7 ?8.0 ma d in = v cc , d out+ = 0 v or d in = gnd, d out? = 0 v lvds output leakage (d out+ , d out? ) power-off leakage i off ?10 1 +10 a v out = v cc or gnd, v cc = 0 v power supply supply current, unloaded i cc 4.0 8.0 ma no load, d in = v cc or gnd supply current, loaded i ccl 7 10 ma d in = v cc or gnd esd protection d out+ , d out? pins 15 kv human body model all pins except d out+ , d out? 4 kv human body model 1 current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are reference d to ground except v od , v od , and v os . 2 the adn4661 is a current mode device and functions within data sheet specif ications only when a resist ive load is applied to t he driver outputs. typical range is 90 to 110 . 3 output short-circuit current (i os ) is specified as magnitude only; minus sign indicates direction only.
adn4661 rev. 0 | page 4 of 12 ac characteristics v cc = 3 v to 3.6 v; r l = 100 ; c l 1 = 15 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. parameter 2 symbol min typ max unit conditions/comments 3 , 4 differential propagation delay high to low t phld 0.3 0.8 1.5 ns see figure 3 and figure 4 differential propagation delay low to high t plhd 0.3 1.1 1.5 ns see figure 3 and figure 4 differential pulse skew |t phld ? t plhd | 5 t skd1 0 0.3 0.7 ns see figure 3 and figure 4 differential part-to-part skew 6 t skd3 0 1.0 ns see figure 3 and figure 4 differential part-to-part skew 7 t skd4 0 1.2 ns see figure 3 and figure 4 rise time t tlh 0.2 0.5 1.0 ns see figure 3 and figure 4 fall time t thl 0.2 0.5 1.0 ns see figure 3 and figure 4 maximum operating frequency 8 f max 350 mhz see figure 3 1 c l includes probe and jig capacitance. 2 ac parameters are guaranteed by design and characterization. 3 generator waveform for all tests, unless otherwise specified: f = 50 mhz, z o = 50 , t tlh 1 ns, and t thl 1 ns. 4 all input voltages are for one channel unless o therwise specified. other inputs are set to gnd. 5 t skd1 = |t phld ? t plhd | is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edg e of the same channel. 6 t skd3 , differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagati on delays. this specification applies to device s at the same v cc and within 5c of each other within the operating temperature range. 7 t skd4 , differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. this specification applies to devices over recommended operating temperatures and voltage ranges , and across process distribution. t skd4 is defined as |maximum ? minimum| differential propagation delay. 8 f max generator input conditions: t tlh = t thl < 1 ns (0% to 100%), 50% duty cycle, 0 v to 3 v. output criteria: duty cycle = 45% to 55%, v od > 250 mv, all channels switching. test circuits and timing diagrams 07876-002 r l /2 r l /2 d in d out+ d out? v cc v cc v os v od v v figure 2. test circuit for driver v od and v os 07876-003 c l c l d in d out+ d out? notes 1. c l includes probe and jig capacitance. signal generator v cc 50 ? 07876-004 d in v diff t plhd t phld v diff = d out+ ?d out? v oh v ol v od 3 v 1.5v 0v (differential) 0v 80% 20% 0v d out+ d out? t tlh t thl figure 4. driver propagation delay and transition time waveforms
adn4661 rev. 0 | page 5 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. all voltages are relative to their respective ground. table 3. parameter rating v cc to gnd ?0.3 v to +4 v input voltage (d in ) to gnd ?0.3 v to v cc + 0.3 v output voltage (d out+ , d out? ) to gnd ?0.3 v to v cc + 0.3 v short-circuit duration (d out+ , d out? ) to gnd continuous operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja soic package ja thermal impedance 149.5c/w reflow soldering peak temperature pb-free 260c 5c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adn4661 rev. 0 | page 6 of 12 pin configuration and fu nction descriptions v cc 1 d in 2 nc 3 gnd 4 d out? 8 d out+ 7 nc 6 nc 5 nc = no connect adn4661 top view (not to scale) 07876-005 figure 5. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 v cc power supply input. the part can be operated from 3.0 v to 3.6 v, and the supply should be decoupled with a 10 f solid tantalum capacitor in parallel with a 0.1 f capacitor to gnd. 2 d in driver logic input. 3 nc no connect. this pin should be left unconnected. 4 gnd ground. reference point for all circuitry on the part. 5 nc no connect. this pin should be left unconnected. 6 nc no connect. this pin should be left unconnected. 7 d out+ noninverting output current driver. when d in is high, current flows out of d out+ . when d in is low, current flows into d out+ . 8 d out? inverting output current driver. when d in is high, current flows into d out? . when d in is low, current flows out of d out? .
adn4661 rev. 0 | page 7 of 12 typical performance characteristics 07876-006 1.415 1.414 1.413 1.412 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output high voltage, v oh ( v) power supply voltage, v cc (v) t a = 25c r l = 100 ? figure 6. output high voltage vs. power supply voltage 07876-007 1.090 1.089 1.088 1.087 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output low voltage, v ol ( v) power supply voltage, v cc (v) t a = 25c r l = 100 ? figure 7. output low voltage vs. power supply voltage 07876-008 ? 3.9 ?4.0 ?4.1 ?4.2 3.0 3.1 3.2 3.3 3.4 3.5 3.6 short-circuit current, i os ( m a) power supply voltage, v cc (v) t a = 25c v in = gnd or v cc v out = 0v figure 8. output short-circuit current vs. power supply voltage 07876-009 325.0 324.2 324.4 324.6 324.8 324.0 3.03.13.23.33.43.53.6 differential output voltage, v od (mv) power supply voltage, v cc (v) t a = 25c r l = 100 ? figure 9. differential output voltage vs. power supply voltage 07876-010 500 300 350 400 450 250 90 100 110 120 130 140 150 differential output voltage, v od (mv) load resistor, r l ( ? ) t a = 25c v cc = 3.3v figure 10. differential output voltage vs. load resistor 07876-011 1.252 1.250 1.251 1.249 3.03.13.23.33.43.53.6 offset voltage, v os (mv) power supply voltage, v cc (v) t a = 25c r l = 100 ? figure 11. offset voltage vs. power supply voltage
adn4661 rev. 0 | page 8 of 12 19 17 15 13 11 9 7 5 0.01 0.1 1 10 100 1k switching frequency (mhz) power supply current, i cc (ma) 07876-012 t a = 25c v cc = 3.3v v in = 0v to 3v c l = 15pf r l = 100 ? figure 12. power supply current vs. switching frequency 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 3.0 3.3 3.6 power supply voltage, v cc (v) power supply current, i cc (ma) 07876-013 t a = 25c f = 1mhz v in = 0v to 3v c l = 15pf r l = 100 ? figure 13. power supply curren t vs. power supply voltage 9 8 7 6 5 ?40 ?15 10 35 60 85 ambient temperature, t a (c) power supply current, i cc (ma) 07876-014 v cc = 3.3v f = 1mhz v in = 0v c l = 15pf r l = 100 ? figure 14. power supply current vs. ambient temperature 07876-015 1200 1000 1100 900 3.0 3.1 3.2 3.3 3.4 3.5 3.6 differential propagation delay (ns) power supply voltage, v cc (v) t phld t plhd t a = 25c f = 1mhz c l = 15pf r l = 100 ? figure 15. differential propagation delay vs. power supply voltage 07876-016 1200 1000 1100 900 differential propagation delay (ns) ambient temperature, t a (c) t phld t plhd ?40 ?20 0 20 40 60 80 100 v cc = 3.3v f = 1mhz c l = 15pf r l = 100 ? figure 16. differential propagation delay vs. ambient temperature 07876-017 100 20 40 60 80 0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 differential skew, t skd1 (ps) power supply voltage, v cc (v) t a = 25c f = 1mhz c l = 15pf r l = 100 ? figure 17. differential skew vs. power supply voltage
adn4661 rev. 0 | page 9 of 12 07876-018 50 10 20 30 40 0 differential skew, t skd1 (ps) ambient temperature, t a (c) ?40 ?20 0 20 40 60 80 100 v cc = 3.3v f = 1mhz c l = 15pf r l = 100 ? figure 18. differential skew vs. ambient temperature 07876-019 400 340 360 380 320 3.0 3.1 3.2 3.3 3.4 3.5 3.6 transition time (ps) power supply voltage, v cc (v) t a = 25c f = 1mhz c l = 15pf r l = 100 ? t tlh t thl figure 19. transition time vs. power supply voltage 07876-020 400 340 360 380 320 transition time (ps) ambient temperature, t a (c) ?40 ?20 0 20 40 60 80 100 t tlh t thl v cc = 3.3v f = 1mhz c l = 15pf r l = 100 ? figure 20. transition time vs. ambient temperature
adn4661 rev. 0 | page 10 of 12 theory of operation the adn4661 is a single line driver for low voltage differential signaling. it takes a single-ended 3 v logic signal and converts it to a differential current output. the data can then be trans- mitted for considerable distances, over media such as a twisted- pair cable or pcb backplane, to an lvds receiver, where it develops a voltage across a terminating resistor, r t . this resistor is chosen to match the characteristic impedance of the medium, typically around 100 . the differential voltage is detected by the receiver and converted back into a single-ended logic signal. when d in is high (logic 1), current flows out of the d out+ pin (current source) through r t and back to the d out? pin (current sink). at the receiver, this current develops a positive differential voltage across r t (with respect to the inverting input) and results in a logic 1 at the receiver output. when d in is low (logic 0), d out+ sinks current and d out? sources current. a negative differen- tial voltage across r t results in a logic 0 at the receiver output. the output drive current is between 2.5 ma and 4.5 ma (typically 3.55 ma), developing between 250 mv and 450 mv across a 100 termination resistor. the received voltage is centered around the receiver offset of 1.2 v. therefore, the noninverting receiver input for logic 1 is typically (1.2 v + [355 mv/2]) = 1.377 v, and the inverting receiver input is (1.2 v ? [355 mv/2]) = 1.023 v. for logic 0, the inverting and noninverting output voltages are reversed. note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across r t is twice the differential voltage. current-mode drivers offer considerable advantages over voltage mode drivers such as rs-422 drivers. the operating current remains fairly constant with increased switching frequency, whereas the current of voltage mode drivers increases exponentially in most cases. this is caused by the overlap as internal gates switch between high and low, which causes currents to flow from the device power supply to ground. a current-mode device simply reverses a constant current between its two outputs, with no significant overlap currents. this is similar to emitter-co upled logic (ecl) and positive emitter-coupled logic (pecl), but without the high quiescent current of ecl and pecl. applications information figure 21 shows a typical application for point-to-point data transmission using the adn4661 as the driver and the lvds receiver. adn4661 lvds receiver 0.1f v cc +3.3 v 10f tantalum + 0.1f v cc +3.3 v d out d in d out+ d out? d in+ d in? 10f tantalum + r t 100 ? gnd gnd 07876-021 figure 21. typical application circuit
adn4661 rev. 0 | page 11 of 12 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 22. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model temperature range packag e description package option adn4661brz 1 ?40c to +85c 8-lead standard small outline package [soic-n] r-8 ADN4661BRZ-REEL7 1 ?40c to +85c 8-lead standard small outline package [soic-n] r-8 1 z = rohs compliant part.
adn4661 rev. 0 | page 12 of 12 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07876-0-12/08(0)

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